TLP and VFTLP Testing of Integrated Circuit ESD Protection

This paper presents electrical methods used to measure and analyze the operation of ESD protection circuits built into every lead of an Integrated Circuit (IC). These circuits clamp voltage threats to sensitive core circuits which enter through each connections to the outside world. Representative samples of each IC are tested for their ESD immunity level to insure a minimum level of protection. Different standards specify electrical waveform parameters which simulate voltage levels, source impedances, and waveforms from different ESD source threats. ESD testing identifies immunity levels on IC's by a simple pass or fail result; but provides no additional data on the failure cause. ESD occurs when a charge that is stored in a capacitive element, discharges into a pin (or lead/ball) of an integrated circuit. There are a number of fundamentally different ESD threats to core circuits. The two basic threats are Human Body Model (HBM) which lasts 150 nanoseconds and the Charged Device Model (CDM) which lasts only a nanosecond or two. ESD protection circuits clamp ESD voltages to an acceptable level and shunt their current to ground. To protect core IC operating circuits, the voltage clamping circuit must turn on at a voltage slightly above that of the signal/data level. ESD protection circuits are located at the outer edges of an IC chip where its leads connect to the outside world. They are placed at the bond pad or directly under it to save expensive silicon surface space. Their only purpose is to protect the operating core circuits by clamping the ESD voltage to harmless levels, and shunting the ESD current harmlessly to ground.